In the current computer architecture as shown in FIG. 1, a chipset 11 is used to control data flows among a central processing unit (CPU) 10, a system memory 13 and a plurality of I/O devices including AGP (Accelerated Graphics Port) and PCI (Peripheral Component Interconnect) devices. The AGP device, for example a graphics accelerator, is electrically connected to the chipset 11 via an AGP slot 14 and an AGP bus 141. The PCI device is electrically connected to the chipset 11 via a PCI slot 12 and a PCI bus 121.
In general, the data transmission rate via an AGP bus is required to at least double the data transmission rate via a common PCI bus in order to assure of high-speed data transmission between the graphics card and the chipset. In the cases that the high-speed graphing functions are not required at all, e.g. for a server or an industrial computer, however, the exclusive AGP transmission mode becomes a redundant design. In order to make use of the devices, an adapter chip 15, in lieu of the AGP slot 14, is coupled to the north bridge chip 110 of the chipset 11 via the AGP bus 141, as shown in FIG. 2. Via the adapter chip 15, a plurality of PCI buses, e.g. two PCI buses 150 and 151 in FIG. 2, can be provided in addition to the PCI slot 12 and the PCI bus 121 the south bridge chip 111 to communicate two PCI devices 171 and 172 with the north bridge chip 110. The adapter chip 15, for example, can be a VPX chipset commercially available from VIA Technologies, Inc. (Taiwan).
Once the AGP device function is completely removed as mentioned above, there would be problems when the high-speed graphing functions are occasionally required.